Creating Multimedia Future Today

Data Compression

This family of products includes a data compressor and a data decompressor. These IP cores use the Lempel–Ziv Ross Williams algorithm, named LZRW3, which is a variant of the LZ77 algorithm.

The compressor and decompressor are designed to operate together, providing a seamless interconnection.

These IP cores target high performance applications. Using current mid-range FPGAs, they can operate at 250 MHz to 300 MHz. The throughput of the compressor is one byte per clock cycle (i.e. 250-300 Mbytes/s). The maximum throughput of the decompressor is 11% smaller.

Part Number Description  
CWdc01
LZRW3 Lossless Data Compressor
CWdc02
LZRW3 Lossless Data Decompressor
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