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Coreworks releases the CWda17 Configurable Digital Audio Serial Output
The CWda17 IP core is a configurable stereo audio interface component designed to output a serial digital audio stream. The CWda17 supports the well known I2S interface format originally developed by Philips and also the Left-Justified or Right-Justified serial audio formats. The CWda17 can also be configured at runtime to support two (16, 20, 24 or 32 bit) audio channels written to two different addresses in an interleaved manner (“dualchannel-interleaving”), two 16-bit audio channels read in parallel from the same register address (“parallel-dualchannel write mode”), or one (16, 20, 24 or 32 bit) audio channel “single-channel” write mode. The audio samples are placed into a transmission FIFO using the CW-Link format. A runtime configurable output stage retrieves the samples from the FIFO and serializes the data to generate the serial audio stream (I2S, Left-Justified, or Right-Justified). The FIFO input is clocked with the bus clock (cw_clk) unrelated to Fs (it must be clocked at a frequency above 2xFs when in dual-channel-interleaving mode, or above Fs for parallel-dualchannels or single-channel write), and the FIFO output is clocked with the serial audio master clock (mclk) at a frequency of 256xFs, where Fs is the sample rate frequency.
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