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FireWorks^™ Architecture

AAC-LC and HE-AAC Audio EncoderAAC-LC and HE-AAC Audio DecoderMPEG-1/2 - Layer I/II Audio EncoderMPEG-1/2 - Layer I/II Audio DecoderAAC-LC Stereo Audio EncoderAAC-LC Audio EncoderAAC-LC Audio DecoderMPEG-1/2 + AAC Audio Decoders

SPDIF-Rx-Pro : Configurable SPDIF-AES3 ReceiverSPDIF-Tx-Pro : Configurable SPDIF-AES3 TransmitterI2S/TDM-Rx-Pro: Configurable Multi-channel Serial Audio ReceiverI2S/TDM-Tx-Pro: Configurable Multi-channel Serial Audio TransmitterI2S/TDM-Rx+Tx-Pro : Configurable Multi-Channel Serial Audio TransceiverI2S/TDM Serial Audio Interface with Asynchronous Sample Rate Conversion

The FireWorks™ is a 5-stage pipeline modified Harvard RISC architecture featuring a high-speed reprogramming interface and specific DSP instructions. This processor has instruction and data caches of configurable size. It can be configured to include instruction extensions (32-bit multiply or multiply/add with 64-bit result and saturation, barrel shifters, additional registers and a serial divider), requiring additional hardware resources. External interrupt requests are supported. The FireWorks does not support exceptions for instructions or data.

The high-speed reprogramming interface can be used to load a program in the memory. In our test environment, it is typically connected to a core that impelements a local area network interface. The prototypes can be controlled by a remote test program implemented with the Remote Access Library (RAL), a software package for building remote data exchange and control applications for cores connected using this infrastructure.

The FireWorks tool kit further features a GNU compiler and tools to convert the executables (.elf files) in program memory models for simulation and implementation. The main features of Fireworks are the following:

• 32-bit data and instruction RISC architecture
• 5-stage pipeline
• Configurable type and number of functional units
• 32-bit ALU
• Configurable number of input and output ports
• Optional Barrel shifter
• Optional integer multiply or multiply/accumulate unit 32-bit operands / 64-bit result and saturation
• Optional serial divider
• 1.31 DMIPS/MHz
• CoreConnect™/OPB or AMBA®/AHB bus interface
• High-speed reprogramming interface
• GNU Binary Utilities
• Networked programming and debugging tools
• Program memory model generator from executable file
• Small area, low power, multi purpose processor
• Network interface allows easy debugging, monitoring and data exchange

List of FireWorks^™ Enabled Cores